A 50.8-53-GHz clock generator using a harmonic-locked PD in 0.13-mu m CMOS

作者：Lee Chihun^*; Cho Lan Chou; Wu Jia Hao; Liu Shen Iuan

来源：IEEE Transactions on Circuits and Systems II-Express Briefs, 2008, 55(5): 404-408.

DOI：10.1109/TCSII.2007.914430

• clock generator
• phase detector
• voltage-controlled oscillator (VCO)
• reference spur

A 50.8-53-GHz clock generator with a quadruplicate-harmonic-locked phase detector (PD) is presented to achieve a low spur and a low reference frequency. The proposed quadruplicate-harmonic-locked PD, a low-voltage Colpitts voltage-controlled oscillator, and a wide-range divide-by-2 divider are also presented. This clock generator has been fabricated in a 0.13-mu m process. The measured reference spur is - 59.88 dBc at 51.02 GHz with an input reference frequency of 199.3 MHz. The area is 0.93 mm x 1 mm with the on-chip loop filter and pads. It dissipates 87 mW without buffers from a 1.5-V supply.

• 出版日期2008-5
• 单位中国科学院电工研究所