Advanced Variance Reduction and Sampling Techniques for Efficient Statistical Timing Analysis

作者：Jaffari Javid^*; Anis Mohab

来源：IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010, 29(12): 1894-1907.

DOI：10.1109/TCAD.2010.2061553

• Control variate
• digital very large scale integration (VLSI) circuits
• quasi-Monte Carlo
• statistical static timing analysis (SSTA)
• timing yield
• variance reduction

The Monte-Carlo (MC) technique is a traditional solution for a reliable statistical analysis, and in contrast to probabilistic methods, it can account for any complicate model. However, a precise analysis that involves a traditional MC-based technique requires many simulation iterations, especially for the extreme quantile points. In this paper, advanced sampling and variance reduction techniques, along with applications for efficient digital circuit timing yield analysis, are studied. Three techniques are proposed: 1) an enhanced quasi-MC-based sampling which generates optimally low-discrepancy samples suitable for yield estimation of digital circuits; 2) an order-statistics based control variate technique that improves the quality of the yield estimations, when a moderate number of samples is needed; and 3) a classical control-variate technique utilized for a variance-reduced critical delay's statistical moment estimation. This solution is shown to be effective even for a very low number of samples.

• 出版日期2010-12