A single-cycle output buffered router with layered switching for Networks-on-Chips

作者：Chen, Yancang^*; Lu, Zhonghai; Xie, Lunguo; Li, Jinwen; Zhang, Minxuan

来源：Computers & Electrical Engineering, 2012, 38(4): 906-916.

DOI：10.1016/j.compeleceng.2012.02.018

We present a single-cycle output buffered router based on layered switching for networks on chips (NoCs). Different from state-of-the-art NoC routers, the router has three important characteristics: (1) It employs layered switching, which implements wormhole on top of virtual cut-through (VCT) switching; (2) In contrast to input buffered architectures, it adopts an output buffered architecture; (3) It is single cycle, meaning that the router pipeline takes only one cycle for all flits. Experimental results show that the router achieves up to 80% of ideal network throughput under uniform random traffic pattern. Compared with wormhole switching, layered switching achieves up to 36.9% latency reduction for 12-flit packets under uniform random traffic with an injection rate of 0.5 flit/cycle/node. Under 65 nm technology synthesized results show that its critical path has only 20 logic gates, and it reduces 11% area compared to the input virtual-channel router with the same buffer capacity.

• 出版日期2012-7
• 单位中国人民解放军国防科学技术大学