A background digital calibration of split-capacitor 16-bit SAR ADC with sub-binary architecture

作者：Cao, Chao; Ye, Qian; Zhu, Zhangming^*; Yang, Yintang

来源：MICROELECTRONICS JOURNAL, 2015, 46(9): 795-800.

DOI：10.1016/j.mejo.2015.06.013

• Digital calibration
• Sub-binary architecture
• Split-capacitor SAR ADC
• High resolution SAR
• LMS algorithm

The paper introduces a sub-binary architecture in 16-bit split-capacitor successive-approximation register (SAR) analog-to-digital converters (ADCs). The redundancy in sub-binary capacitors array provides ways to correct the dynamic errors in conversion procedure with a smaller overall conversion time. So the redundancy can be used to solve the mismatch or parasitic problems in split-capacitor CDAC SAR A background digital calibration method with perturbation is utilized to calibrate the conversion errors. The behavioral simulation and measured results show that the 16-bit SAR ADC performance can be improved after the digital calibration. The prototype was fabricated in 0.18 mu m CMOS process. The INL are -6/7.813 LSB, the DNL are -0.925/1.313 before calibration. After calibration, the INL are -0.813/0.938, the DNL are -0.625/0.688. The measured ENOB is 11.42 bit and SFDR is 79.95 dB before calibration, while the ENOB is 14.46 bit and SFDR is 95.65 dB after calibration.

• 出版日期2015-9
• 单位西安电子科技大学