An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM

作者：Na Taehui^*; Kim Jisu; Song Byungkyu^*; Kim Jung Pill^*; Kang Seung H^*; Jung Seong Ook^*

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(4): 1361-1370.

DOI：10.1109/TVLSI.2015.2453192

• Dual V-ref sensing scheme (DVSS)
• magnetoresistive random access memory (MRAM)
• offset tolerant
• process variation
• sensing margin
• spin-transfer-torque RAM (STT-RAM)

Due to the increased process variation and reduced supply voltage in deep submicrometer technology nodes, an offset-tolerant sensing scheme has become essential. However, most offset-tolerant sensing schemes suffer from inherent performance degradation owing to multiple-stage sensing. In this paper, a dual V-ref sensing scheme (DVSS) that selectively uses an optimal V-ref between Vref+ and Vref- is proposed. This scheme is tolerant to process variations, and can be used as a spin-transfer-torque random access memory. Because of no additional sensing stage, the offset-tolerant sensing is achieved without sacrificing the performance. The optimal V-ref is selected after fabrication, and the calibrated switch control bit, which contains V-ref selection information, is stored permanently in an on-chip nonvolatile latch. Monte Carlo HSPICE simulation results, using an industry-compatible 45-nm model parameters, show that the proposed DVSS achieves a read yield of 98.24% for 32 Mb (6.1 sigma) with 2x faster sensing speed and 1.5x lower read energy per bit compared with the state-of-the-art offset-tolerant sensing scheme.

• 出版日期2016-4