MPSoCBench: A benchmark for high-level evaluation of multiprocessor system-on-chip tools and methodologies

作者：Duenha Liana^*; Madalozzo Guilherme; Santiago Thiago; Moraes Fernando; Azevedo Rodolfo

来源：Journal of Parallel and Distributed Computing, 2016, 95: 138-157.

DOI：10.1016/j.jpdc.2016.03.009

• MPSoC
• Simulation
• Modeling
• DVFS

Recent design methodologies and tools aim at enhancing the design productivity by providing a software development platform before defining the final MPSoC architecture details. Motivated by the lack of MPSoC virtual platforms prototyping integrating both scalable hardware and software in order to create and evaluate new methodologies and tools, we present the MPSoCBench, a scalable set of MPSoCs including four different ISAs (PowerPC, MIPS, SPARC, and ARM) organized in platforms with up to 64 cores, cross-compilers, IPs, interconnections, 17 parallel versions of software from well-known benchmarks, and power consumption estimation for main components (processors, routers, memory, and caches), including DVFS support.

• 出版日期2016-9