A novel source-drain follower for monolithic active pixel sensors

作者:Gao, C.*; Aglieri, G.; Hillemanns, H.; Huang, G.*; Junique, A.; Keil, M.; Kim, D.; Kofarago, M.; Kugathasan, T.; Mager, M.; Tobon, C. A. Marin; Martinengo, P.; Mugnier, H.; Musa, L.; Lee, S.; Reidt, F.; Riedler, P.; Rousset, J.; Sielewicz, K. M.; Snoeys, W.; Sun, X.; Van Hoorne, J. W.; Yang, P.
来源:Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment , 2016, 831: 147-155.
DOI:10.1016/j.nima.2016.03.074

摘要

Monolithic active pixel sensors (MAPS) receive interest in tracking applications in high energy physics as they integrate sensor and readout electronics in one silicon die with potential for lower material budget and cost, and better performance. Source followers (SFs) are widely used for MAPS readout: they increase charge conversion gain 1/C-eff or decrease the effective sensing node capacitance C-eff because the follower action compensates part of the input capacitance. Charge conversion gain is critical for analog power consumption and therefore for material budget in tracking applications, and also has direct system impact. This paper presents a novel source-drain follower (SDF), where both source and drain follow the gate potential improving charge conversion gain. For the inner tracking system (ITS) upgrade of the ALICE experiment at CERN, low material budget is a primary requirement. The SDF circuit was studied as part of the effort to optimize the effective capacitance of the sensing node. The collection electrode, input transistor and routing metal all contribute to C-eff. Reverse sensor bias reduces the collection electrode capacitance. The novel SDF circuit eliminates the contribution of the input transistor to C-eff reduces the routing contribution if additional shielding is introduced, provides a way to estimate the capacitance of the sensor itself, and has a voltage gain closer to unity than the standard SF. The SDF circuit has a somewhat larger area with a somewhat smaller bandwidth, but this is acceptable in most cases. A test chip, manufactured in a 180 nm CMOS image sensor process, implements small prototype pixel matrices in different flavors to compare the standard SF to the novel SF and to the novel SF with additional shielding. The effective sensing node capacitance was measured using a Fe-55 source. Increasing reverse substrate bias from -1 V to -6 V reduces C-eff by 38% and the equivalent noise charge (ENC) by 22% for the standard SF. The SDF provides a further 9% improvement for C-eff and 25% for ENC. The SDF circuit with additional shielding provides 18% improvement for C-eff and combined with -6 V reverse bias yields almost a factor 2.