Memory Latency Hiding by Load Value Speculation for Reconfigurable Computers

作者：Thielmann Benjamin^*; Huthmann Jens; Koch Andreas

来源：ACM Transactions on Reconfigurable Technology and Systems, 2012, 5(3): 13.

DOI：10.1145/2362374.2362377

• Design
• Performance
• FPGA
• high-level language compilation
• speculative execution
• memory interface

Load value speculation has long been proposed as a method to hide the latency of memory accesses. It has seen very limited use in actual processors, often due to the high overhead of reexecuting misspeculated computations. We present PreCoRe, a framework capable of generating application-specific microarchitectures supporting load value speculation on reconfigurable computers. The article examines the lightweight speculation and replay mechanisms, the architecture of the actual data value prediction units as well as the impact on the nonspeculative parts of the memory system. In experiments, using PreCoRe has achieved speedups of up to 2.48 times over nonspeculative implementations.

• 出版日期2012-10