Memory bandwidth efficient hardware architecture for AVS encoder

作者：Ding Dandan^*; Yao Shuo; Yu Lu

来源：IEEE Transactions on Consumer Electronics, 2008, 54(2): 675-680.

DOI：10.1109/TCE.2008.4560146

• AVS
• motion estimation
• memory
• data reuse
• bandwidth

A memory bandwidth efficient architecture for AVS encoder is proposed in this paper. First, simplified ME (Motion Estimation) algorithms are designed to reduce the memory and bandwidth cost. Then a data reuse method with simple control mechanism is proposed to increase the utilization of on-chip memory. The proposed architecture efficiently reduces the bandwidth and memory consumption with acceptable degradation in coding performance. The encoder(1) is implemented with 640 K logic gates in 0.18 mu m(2) CMOS technology and can satisfy real time encoding of 720x576 4:2:0 25fps AVS video at the working frequency of 108MHz.

• 出版日期2008-5
• 单位浙江大学