A 65 nm Temporally Hardened Flip-Flop Circuit

作者：Li, Y. -Q.^*; Wang, H. -B.; Liu, Rui; Chen, Li; Nofal, Issam; Chen, Q. -Y.; He, A. -L.; Guo, Gang; Baeg, Sang H.; Wen, Shi-Jie; Wong, Richard; Wu, Qiong; Chen, Mo

来源：IEEE Transactions on Nuclear Science, 2016, 63(6): 2934-2940.

DOI：10.1109/TNS.2016.2608911

• Flip-flop
• SET
• SEU
• temporal hardening

A guard-gate based flip-flop circuit temporally hardened against single-event effects is presented in this paper. Compared to several existed techniques, the organization of components inside the proposed design allows the improved performance- only one tau (the maximum width of a single-event transient (SET) to tolerate) is added into the setup time. A previously reported low-power delay element is applied, which helps make the proposed design power-efficient. The proposed design was implemented in a 65 nm CMOS bulk technology. Alpha and heavy-ions radiation experiments were performed to characterize its soft-error rates. Experimental results show that the proposed design presents no error with LETs up to 37.3 MeV-cm(2)/mg. Simulation results from the TFIT further validate the experimental results.

• 出版日期2016-12
• 单位中国石油大学（北京）; 中国原子能科学研究院; Saskatchewan; Cisco; Saskatoon