Design of a Low-Power 20Gb/s 1:4 Demultiplexer in 0.18 mu m CMOS

作者：Pan Min; Feng Jun^*

来源：Chinese Journal of Electronics, 2015, 24(1): 71-75.

DOI：10.1049/cje.2015.01.012

• Demultiplexer
• Low power
• Dynamic CMOS logic latch
• Single clock dynamic-loading latch

A low-power multi-phase clock 20Gb/s 1:4 Demultiplexer (DEMUX) without inductors is designed in 0.18 mu m Complementary metal oxide semiconductor (CMOS) process. The 1:4 DEMUX includes two 1:2 DEMUX cells, one 1/2 frequency divider cell, some data and clock buffers. A dynamic CMOS logic latch is used in the 1:2 DEMUX cell and a single clock dynamic-loading latch is used in the 1/2 frequency divider cell. These two kinds of logical structures not only reduce power dissipation and area, but also have an output rail-to-rail level. The rail-to-rail level can offer high noise margin and implement seamless connection without logic level conversion in system integration. The test results show that when the data rate of the input pseudorandom is 20Gb/s and the sequence length is 2(31)-1, this 1:4 DEMUX can work well at a supply voltage of 2V. The output swing is 450mV with external 50 Ohm load and the die size is 0.475 x 0.475 mm(2). The chip power dissipation is 86mW, when four pads connect with a four-channel oscillograph.

• 出版日期2015-1
• 单位东南大学; 合肥工业大学