A low-jitter spread spectrum clock generator using FDMP

作者：Shen Ding Shiuan; Liu Shen Iuan

来源：IEEE Transactions on Circuits and Systems II-Express Briefs, 2007, 54(11): 979-983.

DOI：10.1109/TCSII.2008.919993

• delta-sigma modulator (DSM)
• low jitter
• prescaler
• spread spectrum clock generator (SSCG)

A 1.5 GHz spread spectrum clock generator (SSCG) is realized by a fractional N frequency synthesizer with a third-order delta-sigma modulator and a fractional dual-modulus prescaler (FDMP). This FDMP utilizes a fractional division ratio to have a small phase step to improve the jitter performance. This SSCG has been fabricated in a 0.18 um CMOS process, and it consumes 34.2 mW from a supply of 1.8 V. The measured rms jitter is 5.55 ps and the measured electromagnetic interference reduction amount is 14.77 dB. The measured phase noise is -97.18 dBc/Hz at 1 MHz offset.

• 出版日期2007-11
• 单位中国科学院电工研究所