A Low-Jitter DLL-Based Clock Generator with Two Negative Feedback Loops

作者：Choi Young Shig^*; Park Jong Yoon

来源：Journal of Semiconductor Technology and Science, 2014, 14(4): 457-462.

DOI：10.5573/JSTS.2014.14.4.457

• clock generator
• delay locked loop
• delay-time variance voltage converter

This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal 0.18 mu m CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.

• 出版日期2014-8