Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop

作者：Islam Riadul^*; Guthaus Matthew R

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2015, 62(4): 1156-1164.

DOI：10.1109/TCSI.2015.2402938

• Terms-Clock distribution network
• crosstalk
• current-mode
• flip-flop
• low-power

We propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While current-mode (CM) signaling has been used in one-to-one signals, this is the first usage in a one-to-many clock distribution network. To accomplish this, we create a new high-performance current-mode pulsed flip-flop with enable (CMPFFE) using 45 nm CMOS technology. When the CMPFFE is combined with a CM transmitter, the first CM clock distribution network exhibits 62% lower average power compared to traditional voltage mode clocks.

• 出版日期2015-4