An Ultra-compact Hardware Implementation of SMS4

作者：Shang, Ming^*; Zhang, Qinglong; Liu, Zongbin; Xiang, Ji; Jing, Jiwu

来源：3rd IIAI International Conference on Advanced Applied Informatics (IIAI-AAI), 2014-08-31 To 2014-09-04.

DOI：10.1109/IIAI-AAI.2014.28

• SM4
• FPGA
• resource reutilization
• rescheduling
• IP
• ASIC

SMS4 is widely used in the Chinese National Standard for Wireless LAN WAPI (Wired Authentication and Privacy Infrastructure), and in WLAN WAPI, low-cost and efficient cryptography algorithm implementation is necessary and challenging. This paper proposes an ultra-compact IP core architecture, where the input data is processed in bytes. The proposed architecture further reduces its hardware consumption by reutilizing its resources and rescheduling its procedures. When implemented on the Virtex-4 FPGA platform, the hardware resource consumption of the architecture falls to 30% of the latest work, while the ratio of the throughput to the area remains almost unchanged. It is also implemented on ASIC platform and the synthesis result shows the SMS4 IP core proposed in this paper is quite diminutive and is very suitable for embedded systems.

• 出版日期2014
• 单位中国科学院信息工程研究所; 中国科学院大学; 信息安全国家重点实验室