A Mixed Signal DC Offset Cancellation for VGA of Zero-IF Receiver

作者：Zhao, Yiqiang^*; Wang, Jingshuai; Sheng, Yun

来源：Journal of Circuits, Systems, and Computers, 2017, 26(3): 1750047.

DOI：10.1142/S0218126617500475

• DC offset cancellation
• mixed signal
• near-DC rejection
• zero-IF receiver

This paper proposes a mixed signal DC offset cancellation (DCOC) which does not cause the near-DC rejection for zero-IF receiver. To achieve low output offset efficiently, the DCOC consisting of a comparator, a digital logic controller and compensation voltage generators is used. It utilizes current sources arrays that are controlled by thermometer code to generate the compensation voltage. The proposed DCOC is implemented in GF 0.18 mu m CMOS process. The measurement results show that the proposed calibration method can reduce the offset residue to less than 80 mV and the total calibration time is less than 13 mu s. It only drains 60 mu A from a 3.3 V supply.

• 出版日期2017-3
• 单位天津大学