科研之友
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摘要
An ROM free quadrature direct digital frequency synthesizer (DDFS) was proposed in this paper. The proposed DDFS mainly consists of two adders and two multipliers to generate quadrature outputs The proposed DDFS was Implemented in both cell-base library and ALTERA Stratix EP1S40F780C5 FPGA board for verification
The spurious-free dynamic range (SFDR) measured from FPGA board is about 84 dBc on average The TSMC 0 18 mu m technology is adopted in the cell-based library implementation. The simulated power efficiency is 0.041 mW/MHz averaged for 0 18 pm technology The gate count is about 5384 calculated using the design compiler The maximum clock frequency can reach to 225 MHz.
- 出版日期2010
