Array Architectures for 3-D NAND Flash Memories

作者：Micheloni Rino^*; Aritome Seiichi; Crippa Luca

来源：Proceedings of the IEEE, 2017, 105(9): 1634-1649.

DOI：10.1109/JPROC.2017.2697000

• Charge trap
• floating gate
• staggering of bitline contacts
• staggering of pillars
• 3-D architectures
• 3-D NAND Flash memories

NAND Flash memories have changed and keep changing our lives. In the past two decades, NAND-based systems, in the form of Flash cards and USB keys, have replaced films and floppy disks. But disruption did not stop there. Today, NAND is really ubiquitous, as it plays the role of storage element inside smartphones and tablets; even further, it is now expanding its reach because solid-state drives (SSDs), i.e., drives built with several NAND devices, are replacing hard disk drives (HDDs) in more and more applications. To fuel this continuous evolution, NAND has to remain very aggressive in terms of cost per bit. When approaching 10-nm technologies, planar NAND is running out of steam: industry and academia have worked hard on finding a solution to this problem for more than a decade. Three-dimensional integration turned out to be the most promising alternative, and it is now eventually reaching the market. This paper is about 3-D NAND Flash memories and the related integration challenges. Charge trap and floating gate 3-D technologies will be discussed with the aid of several bird's-eye views. Advanced layout techniques will thoroughly be analyzed. Finally, future scaling trends will be presented.

• 出版日期2017-9