A Resource-Efficient Design for a Reversible Floating Point Adder in Quantum Computing

作者：Trung Duc Nguyen^*; Van Meter Rodney

来源：ACM Journal on Emerging Technologies in Computing Systems, 2014, 11(2): 13.

DOI：10.1145/2629525

• Reversible circuit
• quantum computing
• low-power computing
• nano technology
• IEEE-754 specification
• floating-point arithmetic

Reversible logic has applications in low-power computing and quantum computing. However, there are few existing designs for reversible floating-point adders and none suitable for quantum computation. In this article, we propose a resource-efficient reversible floating-point adder, suitable for binary quantum computation, improving the design of Nachtigal et al. [2011]. Our work focuses on improving the reversible designs of the alignment unit and the normalization unit, which are the most expensive parts. By changing a few elements of the existing algorithm, including the circuit designs of the RLZC (reversible leading zero counter) and converter, we have reduced the cost by about 68%. We also propose quantum designs adapted to use gates from fault-tolerant libraries. The KQ for our fault-tolerant design is almost 60 times as expensive as for a 32-bit fixed-point addition. We note that the floating-point representation makes in-place, truly reversible arithmetic impossible, requiring us to retain both inputs, which limits the sustainability of its use for quantum computation.

• 出版日期2014-11