An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing

作者：Cheng Kuo Hsing^*; Hong Kai Wei; Hsu Chi Fa; Jiang Bo Qian

来源：IEEE Transactions on Very Large Scale Integration Systems, 2012, 20(10): 1818-1827.

DOI：10.1109/TVLSI.2011.2166092

• Arbitrary duty cycle
• clock synchronization buffer (CSB)
• fast locking
• one cycle dynamic locking
• synchronous mirror delay (SMD)

This paper proposes an all-digital clock synchronization buffer (CSB) with one-cycle dynamic synchronization. The CSB synchronizes the input and output clocks in three clock cycles but maintains one cycle at fastest operating frequency. The CSB achieves one-cycle dynamic locking and synchronizes the dynamic frequencies with a modified structure. The CSB compensates for dynamic phase error with a modified fine-tuned circuit. The chip is fabricated using a 130-nm standard CMOS process. Its operating frequency range is between 300 MHz and 800 MHz. The power consumption and RMS jitter are 2.4 mW and 2.25 ps at 800 MHz, respectively. The active area of this chip is 0.015 mm(2).

• 出版日期2012-10
• 单位中央民族大学