Area-delay efficient parallel architecture for Fermat number transform

作者：Li Shuguo^*; Zhang Jian

来源：IEICE Electronics Express, 2009, 6(8): 449-455.

DOI：10.1587/elex.6.449

• Fermat number transform
• diminished-1 number system
• code conversion
• butterfly operation
• carry-save adder

The parallel Fermat number transform (FNT) architecture is usually implemented with the code conversion (CC) and the butterfly operation (BO) in the diminished-1 number system. However, both the CC and the BO require too much area and delay due to modulo 2(n) 1 carry-propagation addition. In this paper, we propose a novel parallel FNT architecture with the root of unity 2 which is mainly composed of carry-save code conversion (CSCC) and carry-save butterfly operation (CSBO). The CSCC and the CSBO remove the carry-propagation addition by exploiting the property of carry-save adders. Thus the proposed FNT architecture requires less area and delay than the previous one. Synthesis results using 0.13-mu m CMOS standard cells library demonstrate the superiority of the resulting architecture against the previously reported solution.

• 出版日期2009-4-25
• 单位清华大学