A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4x Faster Clock Frequency and > 6x Higher Restore Speed

作者：Wang, Zhibo; Liu, Yongpan^*; Lee, Albert; Su, Fang; Lo, Chieh-Pu; Yuan, Zhe; Li, Jinyang; Lin, Chien-Chen; Chen, Wei-Hao; Chiu, Hsiao-Yun; Lin, Wei-En; King, Ya-Chin; Lin, Chrong-Jung; Amiri, Pedram Khalili; Wang, Kang-Lung; Chang, Meng-Fan; Yang, Huazhong

来源：IEEE Journal of Solid-State Circuits, 2017, 52(10): 2769-2785.

DOI：10.1109/JSSC.2017.2724024

• Nonvolatile processor (NVP)
• nonvolatile flip-flops (nvFF)
• nonvolatile SRAM (nvSRAM)
• self-write termination (SWT)
• time-space domain adaption

With an ever-increasing demand for energy efficiency, processors with instant-on and zero leakage features are highly appreciated in energy harvesting as well as "normally off" applications. Recently, zero-standby power and fast switching nonvolatile processors (NVPs) have been proposed based on emerging nonvolatile memories (NVMs), such as ferroelectric RAM or spin-transfer-torque magnetic RAM. However, previous NVPs store all data to NVM upon every power interruption, resulting in high-energy consumption and degraded NVM endurance. This paper presents a 65-nm fully CMOS-logic-compatible ReRAM-based NVP supporting time-space domain adaption. It incorporates adaptive nonvolatile controller, nonvolatile flip-flops, and nonvolatile static random access memory (nvSRAM) with self-write termination. Data redundancy in both time and space domain is fully exploited to reduce store/restore time/energy and boost clock frequency. The NVP operates at > 100 MHz and achieves 20 ns/0.45 nJ restore time/energy, realizing > 6x and > 6000x higher speed and energy efficiency of restore and > 4x faster compared with that of state of the art.

• 出版日期2017-10
• 单位清华大学