A Multiphase-Output Delay-Locked Loop With a Novel Start-Controlled Phase/Frequency Detector

作者：Chang Robert Chen Hao^*; Chen Hou Ming; Huano Po Jen

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2008, 55(9): 2483-2490.

DOI：10.1109/TCSI.2008.920088

• Multiphase-output delay-locked loop
• NAND-resettable dynamic D-flip-flop
• phase/frequency detector
• voltage-controlled delay element

This paper presents a multiphase-output delay-locked loop (MODLL). The proposed phase/frequency detector (PFD) utilizes a new NAND-resettable dynamic D-flip-flop (DFF) circuit to achieve a shorter reset path. Thus, lower power consumption and higher speed can be obtained. The proposed voltage-controlled delay element used in this design can operate at a lower supply voltage and overcome the dead-band issue of the voltage-controlled delay line. An experimental multiphase-output DLL was designed and fabricated using a TSMC 0.35-mu m 2P4M CMOS process. The delay-locked loop (DLL) power consumption is 3.4 mW with a 2 V supply and a 100 MHz input. The measured rms and peak-to-peak jitters are 17.575 ps and 145 ps, respectively. In addition, the supply voltage of the experimental multiphase-output DLL can vary from 1.5 V to 2.5 V without causing malfunctions. The active area is 426 mu m x 381 mu m.

• 出版日期2008-10