A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop

作者：Levantino Salvatore; Marucci Giovanni; Marzin Giovanni; Fenaroli Andrea; Samori Carlo; Lacaita Andrea L

来源：IEEE Journal of Solid-State Circuits, 2015, 50(11): 2678-2691.

DOI：10.1109/JSSC.2015.2473667

• ADPLL
• bang-bang
• CMOS
• delay locked loop
• digital PLL
• frequency synthesis
• jitter
• LMS
• offset
• phase locked loop
• phase noise
• RF
• TDC

Although multiplying delay-locked loops allow clock frequency multiplication with very low phase noise and jitter, their application has been so far limited to integer-N multiplication, and the achieved reference-spur performance has been typically limited by time offsets. This paper presents the first published multiplying delay-locked loop achieving fine fractional-N frequency resolution, and introduces an automatic cancellation of the phase detector offset. Both capabilities are enabled by insertion of a digital-to-time converter in the reference path. The proposed synthesizer, implemented in a standard 65 nm CMOS process, occupies a core area of 0.09 mm(2), and generates a frequency ranging between 1.6 and 1.9 GHz with a 190 Hz resolution from a 50 MHz quartz-based reference oscillator. In fractional-N mode, the integrated RMS jitter, including random and deterministic components, is below 1.4 ps at 3 mW power consumption, leading to a jitter-power figure of merit of -232 dB. In integer-N mode, the circuit achieves RMS jitter of 0.47 ps at 2.4 mW power and figure of merit of -243 dB. Thanks to the adoption of the automatic offset cancellation, the reference-spur level is reduced from -32 to -55 dBc.

• 出版日期2015-11