A novel 10-transisitor low-power high-speed full adder cell

作者：Lu, JM^*; Shu, Y; Lin, ZH; Wang, L

来源：6th International Conference on Solid-State and Integrated-Circuit Technology, China,Shanghai, 2001-10-22 to 2001-10-25.

A novel high-speed low-power 10-transistor 1-bit full-adder cell is proposed in this paper. The critical path consists of an inverter, an XOR or XNOR gate and one pass transistor. The cell offers higher speed, lower power consumption and lower area than the standard implementations of the 1-bit full-adder cell. A prototype of the proposed adder cell in 0.35um technology has a delay time of 0.2417ns. It also exhibits low average dissipation of 4.936*10(-5) watt at frequency of 100MHz. Simulation results have shown better performance over the standard implementations.

• 出版日期2001
• 单位上海交通大学