A 25 Gb/s 3D-Integrated CMOS/Silicon-Photonic Receiver for Low-Power High-Sensitivity Optical Communication

作者：Saeedi Saman^*; Menezo Sylvie; Pares Gabriel; Emami Azita

来源：Journal of Lightwave Technology, 2016, 34(12): 2924-2933.

DOI：10.1109/JLT.2015.2494060

• energy efficiency
• optical receivers
• sensitivity
• silicon photonics
• 3D-integration

Integrating optical receivers based on double-sampling architecture exhibit a low-power alternative to those designed around transimpedance amplifiers (TIA). In this paper, we present a 3D-integrated CMOS/silicon-photonic optical receiver. The receiver features a low-bandwidth TIA integrating front-end double-sampling technique and dynamic offset modulation. The copper-pillar-based 3D-integration technology used here enables ultralow parasitics and 40 mu m pitch for interconnection. We study different tradeoffs in designing an optical receiver and how to choose between a full-bandwidth TIA front-end and integrating architecture using a resistive front-end or a low-bandwidth TIA front-end. The design methodology is supported by measurements of two 3D-integrated prototypes based on a conventional TIA and a double-sampling integrating receiver. The proposed receiver architecture achieves -14.9 dBm of sensitivity and energy efficiency of 170 fJ/b at 25 Gb/s, while the conventional receiver achieves a sensitivity of -10.4 dBm and energy efficiency of 260 fJ/b at 21.2 Gb/s.

• 出版日期2016-6-15
• 单位中国地震局