A Digital DLL with 4-Cycle Lock Time and 1/4 NAND-Delay Accuracy

作者：Kim Sung Yong; Jin Xuefan; Chun Jung Hoon^*; Kwon Kee Won

来源：Journal of Semiconductor Technology and Science, 2016, 16(4): 387-394.

DOI：10.5573/JSTS.2016.16.4.387

• Delay-locked loop
• DLL
• multi-dither-free phase detector
• fast lock
• merged dual delay line
• region accumulator

This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 nm CMOS process, the proposed DLL occupies 0.0432 mm(2), and consumes 3.7 mW from a 1.2-V supply at 2 GHz.

• 出版日期2016-8