A Study of BER-Optimal ADC-Based Receiver for Serial Links

作者：Lin Yingyan^*; Keel Min Sun; Faust Adam; Xu Aolin; Shanbhag Naresh R; Rosenbaum Elyse; Singer Andrew C

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2016, 63(5): 693-704.

DOI：10.1109/TCSI.2016.2529284

• Analog-to-digital converter
• bit-error-rate
• energy efficiency
• mixed-signal
• serial links

Analog-to-digital converter (ADC)-based multi-Gb/s serial link receivers have gained increasing attention in the back-plane community due to the desire for higher I/O throughput, ease of design portability, and flexibility. However, the power dissipation in such receivers is dominated by the ADC. ADCs in serial links employ signal-to-noise-and-distortion ratio (SNDR) and effective-number-of-bit (ENOB) as performance metrics as these are the standard for generic ADC design. This paper studies the use of information-based metrics such as bit-error-rate (BER) to design a BER-optimal ADC (BOA) for serial links. Channel parameters such as the m-clustering value and the threshold non-uniformity metric h(t) are introduced and employed to quantify the BER improvement achieved by a BOA over a conventional uniform ADC (CUA) in a receiver. Analytical expressions for BER improvement are derived and validated through simulations. A prototype BOA is designed, fabricated and tested in a 1.2 V, 90 nm LP CMOS process to verify the results of this study. BOA's variable-threshold and variable-resolution configurations are implemented via an 8-bit single-core, multiple-output passive digital-to-analog converter (DAC), which incurs an additional power overhead of < 0.1% (approximately 50 mu W). Measurement results show examples in which the BER achieved by the 3-bit BOA receiver is lower by a factor of 10(9) and 10(10), as compared to the 4-bit and 3-bit CUA receivers, respectively, at a data rate of 4-Gb/s and a transmitted signal amplitude of 180 mVppd.

• 出版日期2016-5