Modeling of enclosed-gate layout transistors as ESD protection device based on conformal mapping method

作者：Zhang Jia; Yang Haigang; Sun Jiabin; Yu Le; Wei Yuanfeng; Institute of Electronics Chinese Academy of Sciences; University of Chinese Academy of Sciences

来源：Chinese Journal of Semiconductors, 2014, 35(08): 125-131.

DOI：10.1088/1674-4926/35/8/085001

• electrostatic discharge
• enclosed-gate layout transistor
• modeling
• conformal mapping

This paper proposes a novel technique for modeling the electrostatic discharge(ESD) characteristic of the enclosed-gate layout transistors(ELTs). The model consists of an ELT, a parasitic bipolar transistor, and a substrate resistor. The ELT is decomposed into edge and corner transistors by solving the electrostatic field problem through the conformal mapping method, and these transistors are separately modeled by BSIM(Berkeley Shortchannel IGFET Model). Fast simulation speed and easy implementation is obtained as the model can be incorporated into standard SPICE simulation. The model parameters are extracted from the critical point of the snapback curve,and simulation results are presented and compared to experimental data for verification.

• 出版日期2014-8-15
• 单位中国科学院大学