A 40-Gb/s 14-mW CMOS Wireline Receiver

作者：Manian Abishek^*; Razavi Behzad

来源：IEEE Journal of Solid-State Circuits, 2017, 52(9): 2407-2421.

DOI：10.1109/JSSC.2017.2705913

• Charge steering
• clock and data recovery (CDR)
• decision feedback
• discrete time
• equalizer
• linear equalizer
• phase detector (PD)

A 40-Gb/s receiver includes a continuous-time linear equalizer, a discrete-time linear equalizer, a two-tap decision-feedback equalizer, a clock and data recovery circuit, and a one-to-four deserializer. Hardware minimization and charge steering techniques are extensively used to reduce the power consumption by a factor of ten. Fabricated in 45-nm CMOS technology, the receiver exhibits a bathtub curve opening of 0.28 UI with a recovered clock jitter of 0.5 ps(rms).

• 出版日期2017-9