Accelerated and Reliable Analog Circuits Yield Analysis Using SMT Solving Techniques

作者：Lahiouel Ons^*; Zaki Mohamed H; Tahar Sofiene

来源：IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, 37(3): 517-530.

DOI：10.1109/TCAD.2017.2651807

• Analog circuit
• interval arithmetic
• process variations
• satisfiability modulo theory (SMT)
• surrogate model
• yield

Existing yield analysis methods are computationally expensive and generally encounter challenges with highdimensional process parameters space. In this paper, we propose a new method for accelerated and reliable computation of parametric yield that combines the advantages of sparse regression and satisfiability modulo theory (SMT) solving techniques, and avoids issues in both. The key idea is to characterize the failure regions as a collection of hyperrectangles in the parameters space. Toward this goal, the method constructs sparse polynomial models based on adaptive least absolute shrinkage and selection operator to find low degree approximations of the circuit performances. A procedure inspired by statistical model checking is then introduced to assess the model accuracy. Given the constructed models, an SMT-based solving algorithm is employed to locate the failure hyperrectangles in the parameters space. The yield estimation is based on a geometric calculation of probabilistic volumes subtended by the located hyperrectangles. We demonstrate the effectiveness of our method using circuits that require expensive run-time simulation during yield evaluation. They include: an integrated ring oscillator, a 6T static RAM cell and a multistage fully-differential amplifier. Experimental results show that the proposed method is suitable for handling problems with tens of process parameters. Meanwhile, it can provide 5x-2000x speed-up over Monte Carlo methods, when a high prediction accuracy is required.

• 出版日期2018-3