Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure

作者：Yoshimoto Shusuke^*; Amashita Takuro; Okumura Shunsuke; Kawaguchi Hiroshi; Yoshimoto Masahiko

来源：IEICE - Transactions on Electronics, 2012, E95C(10): 1675-1681.

DOI：10.1587/transele.E95.C.1675

• SRAM
• soft error multiple-bit upset (MBU)
• single-event upset (SEU)
• error correction coding (ECC)
• alpha particle
• neutron particle

This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves low-power operation, which is often preferred for low-power/low-voltage applications. However, the conventional 81 SRAM with the divided wordline structure engenders MBUs because all bits in the same word are physically adjoining. Consequently, it is difficult to apply an error correction coding (ECC) technique to it. In this paper, we propose a new 81 cell layout pattern that separates internal latches in SRAM cells using both an n-well and a p-substrate. We saw that a SEU cross section of nMOS is 3.5-4.5 times higher than that of pMOS (SEU: single event upset; a cross section signifies a sensitive area to soft error effects). By using a soft-error simulator, iRoC TFIT, we confirmed that the proposed 81 cell has better neutron-induced MBU tolerance. The simulator includes soft-error measurement data in a commercial 65-nm process. The MBU in the proposed 81 SRAM is improved by 90.70% and the MBU soft error rate (SER) is decreased to 3.46 FIT at 0.9 V when ECC is implemented (FIT: failure in time). Additionally, we conducted Synopsys 3-0 TCAD simulation, which indicates that the linear energy transfer (LET) threshold in SEU is also improved by 66% in the proposed 81 SRAM by a common-mode effect.

• 出版日期2012-10