A 5-BIT 500-MS/S FLASH ADC USING TIME-DOMAIN COMPARISON

作者：Min Young Jae^*; Kim Hoon Ki; Kim Chulwoo; Kim Soo Won; Kim Gil Su

来源：Journal of Circuits, Systems, and Computers, 2012, 21(8): 1240023.

DOI：10.1142/S0218126612400233

• Analog-to-digital converter
• time-domain comparison
• flash converter
• voltage-to-time converter

A 5-bit 500-MS/s time-domain flash ADC is presented. The proposed ADC consists of a reference resistor ladder, two voltage-to-time converter arrays, a time-domain comparator array and a digital encoder without sample-and-hold. In order to achieve low-power consumption with high conversion-speed and to enhance design reusability in terms of a highly digital implementation with more regular mask patterns, the time-domain comparison is devised in the flash ADC. The prototype has been implemented and fabricated in a standard 0.18 mu m CMOS technology and occupies 0.132mm(2) without pads. The measured SNDR and SFDR up to the Nyquist frequency are 26.6 dB and 35.1 dB, respectively. And the peak DNL and INL are measured as 0.43 LSB and 0.58 LSB, respectively. The prototype consumes 8mW with a 1.8-V supply voltage.

• 出版日期2012-12