A Study of Self-Aligned Nitride Erasable OTP Cell by 45-nm CMOS Fully Compatible Process

作者：Huang Chia En^*; Chen Ying Je; Lai Han Chao; King Ya Chin; Lin Chrong Jung

来源：IEEE Transactions on Electron Devices, 2009, 56(6): 1228-1234.

DOI：10.1109/TED.2009.2018169

• Logic compatible
• nonvolatile memory (NVM)
• p-channel
• self-aligned nitride (SAN)

This brief proposes a new 45-nm erasable one-time programming cell with a self-aligned nitride (SAN) storage node for logic nonvolatile memory (NVM) applications. The CMOS fully logic-compatible cell was successfully demonstrated using 45-nm CMOS technology with a very small cell size of 0.1188 mu m(2). This cell-adapting source-side-injection programming scheme has a wide on/off window and superior program efficiency. The SAN cell with five terminals for various operational conditions uses an asymmetrical read voltage to verify the position of the stored charge. This cell also exhibits excellent data retention capability even when the thickness of the logic gate oxide is less than 20 A, and the gate length is shorter than 40 nm. This new cell provides a promising solution for logic NVM beyond a 90-nm node.

• 出版日期2009-6
• 单位中国科学院电工研究所; 清华大学