Drive Current Enhancement in TFET by Dual Source Region

作者：Jiang Zhi^*; Zhuang Yiqi; Li Cong; Wang Ping; Liu Yuqi

来源：Journal of Electrical and Computer Engineering, 2015, 2015: 1-11.

DOI：10.1155/2015/905718

• Drain-to-source voltages
• Drive current enhancement
• Electrons and holes
• Energy delay product
• Gate source capacitance
• Gate-drain capacitance
• Gate-to-source voltages
• Tunneling field-effect transistors

<jats:p>This paper presents tunneling field-effect transistor (TFET) with dual source regions. It explores the physics of drive current enhancement. The novel approach of dual source provides an effective technique for enhancing the drive current. It is found that this structure can offer four tunneling junctions by increasing a source region. Meanwhile, the dual source structure does not influence the excellent features of threshold slope (SS) of TFET. The number of the electrons and holes would be doubled by going through the tunneling junctions on the original basis. The overlap length of gate-source is also studied. The dependence of gate-drain capacitance<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="M1"><mml:mrow><mml:msub><mml:mrow><mml:mi>C</mml:mi></mml:mrow><mml:mrow><mml:mtext>gd</mml:mtext></mml:mrow></mml:msub></mml:mrow></mml:math>and gate-source capacitance<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="M2"><mml:mrow><mml:msub><mml:mrow><mml:mi>C</mml:mi></mml:mrow><mml:mrow><mml:mtext>gs</mml:mtext></mml:mrow></mml:msub></mml:mrow></mml:math>on gate-to-source voltage<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="M3"><mml:mrow><mml:msub><mml:mrow><mml:mi>V</mml:mi></mml:mrow><mml:mrow><mml:mtext>gs</mml:mtext></mml:mrow></mml:msub></mml:mrow></mml:math>and drain-to-source voltage<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="M4"><mml:mrow><mml:msub><mml:mrow><mml:mi>V</mml:mi></mml:mrow><mml:mrow><mml:mtext>ds</mml:mtext></mml:mrow></mml:msub></mml:mrow></mml:math>was further investigated. There are simulation setups and methodology used for the dual source TFET (DS-TFET) assessment, including delay time, total energy per operation, and energy-delay product. It is confirmed that the proposed TFET has strong potentials for VLSI.</jats:p>

• 出版日期2015-1-21
• 单位西安电子科技大学