A 6-bit active digital phase shifter

作者：Asoodeha Alireza^*; Atarodi Mojtaba

来源：IEICE Electronics Express, 2011, 8(3): 121-128.

DOI：10.1587/elex.8.121

• active phase shifters
• phased arrays
• quadrature networks

This paper presents the design of a 6-bit active digital phase shifter in 0.18-mu m CMOS technology. The active phase shifter synthesizes the required phase using a phase interpolation process by adding quadrature phased input signals. It uses a new quadrature all-pass filter for quadrature signaling with a wide bandwidth and low phase error. The phase shifter has simulated RMS phase error of <0.85 degrees at 2.4-5 GHz. The average voltage gain ranges from 1.7 dB at 2.4 GHz to -0.14 dB at 5 GHz. Input P1 dB is typically 1.3 +/- 0.9 dBm at 3.5 GHz for overall phase states.

• 出版日期2011-2-10