A LOW POWER 13-BIT 50MS/s RECIRCULATING PIPELINE ANALOG TO DIGITAL CONVERTER

作者：Esmaili Arash^*; Babazadeh Hadiseh; Hadidi Khayrollah; Khoei Abdollah

来源：Journal of Circuits, Systems, and Computers, 2014, 23(6): 1450090.

DOI：10.1142/S021812661450090X

• Analog-to-digital converter
• comparator
• data converter
• digital-to-analog converter
• sample and hold

A 13-bit analog-to-digital converter (ADC) is designed in 0.35 mu m CMOS technology that reduces the power consumption through sharing the resources between pipeline stages. Using a dummy sample-and-hold (S/H) and recirculating concept the requirements for the first stage are relaxed and the design restrictions are resolved. This ADC does not use a dedicated S/H and reaches a speed of 50 MS/s. The design is tested with TSMC mixed-signal 0.35 mu m technology and post layout simulations shows over 75 dB Signal-to-Noise and Distortion-Ratio (SNDR) and over 85 dB Spurious Free Dynamic Range (SFDR) at the Nyquist frequency. The designed chip occupies an area of 1.3 mm-0.7 mm and consumes 164mW power at Nyquist from a 3.3V supply.

• 出版日期2014-7