A Reconfigurable Vernier Time-to-Digital Converter With 2-D Spiral Comparator Array and Second-Order Delta Sigma Linearization

作者：Wang Hechen^*; Dai Fa Foster; Wang Hua^*

来源：IEEE Journal of Solid-State Circuits, 2018, 53(3): 738-749.

DOI：10.1109/JSSC.2017.2788872

• Delta Sigma modulation
• autocalibration
• differential nonlinearity (DNL)
• digital phase-locked loop (DPLL)
• integral nonlinearity (INL)
• linearization
• time-to-digital converter (TDC)
• Vernier TDC

This paper presents an 8-bit 1.25-ps resolution reconfigurable Vernier time-to-digital converter (TDC) with a 2-D spiral comparator array and Delta Sigma modulators for linearization. The proposed spiral 2-D comparator array improves both linearity and detection range of the TDC. The quantization errors introduced by digitally tuning delay cells are minimized by using a 2nd-order AI modulator. The folding point errors commonly seen in 2-D comparator arrays are randomized by using a reconfigurable comparator array controlled by the output of a 2nd-order Delta Sigma modulator. The prototype TDC fabricated in a 45-nm silicon on insulator technology consumes 70- to 690-mu W power under a 1-V supply at 80-MHz conversion rate. The measured maximum differential nonlinearity/integral nonlinearity across its detectable range are 135/1.03 ps without the linearization techniques and 031/0.4 ps with the proposed linearization techniques, respectively.

• 出版日期2018-3