An ultra low power and low complexity all digital PLL with a high resolution digitally controlled oscillator

作者：Abadian Arash^*; Lotfizad Mojtaba; Ghaznavi Ghoushchi M B; Majd Nasser Erfani

来源：IEICE Electronics Express, 2011, 8(21): 1801-1807.

DOI：10.1587/elex.8.1801

• all digital phase locked-loop
• digitally controlled oscillator
• glitch removal
• low power
• low complexity

In this letter, a new all digital phase locked loop (ADPLL) is proposed. The proposed ADPLL is introduced a new locking procedure with low complexity which results in an ultra low power design. The design uses only two up-down counters for finding the reference frequency. An efficient glitch removal filter and a new low power DCO are also introduced in this letter. The DCO achieves a reasonably high resolution of 1 ps. The power consumption of the proposed ADPLL at 500MHz frequency is 820 mu W. The proposed ADPLL is simulated in 180nm CMOS with Hspice and verified by MATLAB.

• 出版日期2011-11-10