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摘要
The An AC current induced electro-migration (EM) on clock and logic signals becomes a significant problem even in the presence of reverse-recovery effect. Compared to power network, clock and logic signal interconnects are much narrower and suffer from fast switching and large driving current from FinFETs. Thus, the high current density on those signal interconnects can cause a serious failure. In this paper, we analyze EM on signal interconnects in 16 nm FinFET design, and characterize the impact of process variations, e.g., lithography and etch process, CMP (chemical-mechanical polishing) process, redundant via, etc. We also analyze signal-line EM with transistor-level PVT (process-voltage-temperature) variation corners. Then we optimize the signal lines with various design approaches to mitigate EM problem in 16 nm design.
- 出版日期2016-5
