Fabrication and Comparison of Bumpless Wafer-on-Wafer Integration and Bump-Containing Chip-on-Chip Integration

作者：Guan, Yong^*; Zhu, Yunhui; Ma, Shenglin; Zeng, Qinghua; Chen, Jing; Jin, Yufeng

来源：IEEE Transactions on Components, Packaging and Manufacturing Technology, 2017, 7(7): 1011-1019.

DOI：10.1109/TCPMT.2017.2695647

• 3-D packaging
• chip-on-chip (CoC) integration
• reliability
• through silicon via (TSV)
• wafer-on-wafer (WoW) integration

This paper develops a bumpless wafer-on-wafer (WoW) memory integration approach in order to increase its throughput and reliability without sacrificing the electrical and mechanical performances compared to the bump-containing chip-on-chip (CoC) integration. The features are that through silicon vias are bottom-up filled after multilayer wafers bonding and connected to the predeposited redistribution layers on the front side of each wafer simultaneously. A given mass of four-layer bumpless WoW integration samples and bump-containing CoC integration samples is fabricated. The electrical testing, X-ray inspection, cross-section observation, stress testing, and thermal cycling testing are employed in order to compare the characterization of the two integration approaches. All test results support that there is a better performance, higher throughput, and lower cost in the proposed bumpless WoW integration approach, which indicates that this proposed approach may be a good candidate for memories-stacking application.

• 出版日期2017-7
• 单位北京大学深圳研究生院; 北京大学; 厦门大学