Path-Directed Abstraction and Refinement for SAT-Based Design Debugging

作者：Keng Brian^*; Veneris Andreas

来源：IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013, 32(10): 1609-1622.

DOI：10.1109/TCAD.2013.2263036

• Abstraction
• debugging
• diagnosis
• refinement
• register transfer level (RTL)
• verification
• very large scale integration

Functional verification has become one of the most time-consuming tasks in the very large scale integration design flow accounting for up to 57% of the total project time. The largest component of this task is that of design debugging due to its resource-intensive manual nature. With the ever growing size of modern designs and their error traces, the complexity of the debugging problem poses a great challenge to automated debugging techniques. To overcome this challenge, this paper introduces a novel path-directed abstraction and refinement algorithm for design debugging to manage excessive error trace lengths. A sliding window of the error trace is iteratively analyzed in a time-windowing framework, which is made possible by the use of the path-directed abstraction. This abstraction forms a concise approximation of nonmodeled parts of the error trace while simultaneously providing an efficient representation for refinement. The result is an algorithm that dramatically reduces the memory requirements of debugging while mitigating the incomplete results of past techniques. Experimental results on industrial designs with long error traces show that the proposed approach can analyze traces that are 64.6% longer while simultaneously decreasing peak memory usage compared to previous work.

• 出版日期2013-10