Built-in parasitic-diode-based charge injection technique enhancing data retention of gain cell DRAM

作者：Chung Yeonbae^*; Cheng Weijie; Das Hritom

来源：Electronics Letters, 2015, 51(23): 1854-1855.

DOI：10.1049/el.2015.2237

A gain cell embedded dynamic random access memory (eDRAM) with a noble charge injection technique is presented. The gain memory cell is composed of dual-threshold two logic N-type MOSs implemented in a generic triple-well CMOS process. A negative-voltage toggle on the parasitic junction diode formed between the pocket p-well and the cell data node couples up the cell storage voltages. It results in a much enhanced retention time in a compact bit area. Moreover, the technique exhibits much strong immunity from the write disturbance. Measured results at 85 degrees C from a 110 nm 64 kbit prototype eDRAM incorporating the proposed technique demonstrate 69% enhanced retention time and 86% smaller write disturbance loss compared with the conventional one.

• 出版日期2015-11-5