A 0.6 V 100 KS/s 8-10 b resolution configurable SAR ADC in 0.18 mu m CMOS

作者：Zhu, Zhangming; Xiao, Yu^*; Wang, Weitie; Wang, Qiyu; Yang, Yintang

来源：Analog Integrated Circuits and Signal Processing, 2013, 75(2): 335-342.

DOI：10.1007/s10470-013-0062-6

• Successive approximation register (SAR) A/D converter
• Ultra-low power
• Configurable
• Low voltage
• CMOS

A resolution configurable ultra-low power SAR ADC in 0.18 mu m CMOS process is presented. The proposed ADC has maximum sampling rate of 100 KS/s with configurable resolution from 8 to 10 b and operates at a supply of 0.6 V. Two-stage bootstrapped switch and voltage boosting techniques are introduced to improve the performance of the ADC at low voltage. To reduce the power consumption of the analog components of the ADC, monotonic capacitor switching procedure and fully dynamic comparator are utilized. The implementation of dynamic logic further reduces the power of the digital circuits. Post-layout simulation results show that the proposed SAR ADC consumes 521 nW and achieves an SNDR of 60.54 dB at 10 b mode, resulting in an ultra-low figure-of-merit of 6.0 fJ/conversion-step. The ADC core occupies an active area of only 350 x 280 mu m(2).

• 出版日期2013-5
• 单位西安电子科技大学