科研之友
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摘要
This work presents the design of an optimized power amplifier using Complementary LDMOS (CLDMOS) with 5 mu m gate length. Final results show that the high performance CLDMOS amplifier has been achieved using the optimization of various device parameters and the circuit bias conditions. Optimization of the drift length and the drift area doping in device parameters have been done for both P type LDMOS (PLDMOS) and N type LDMOS (NLD-MOS) for various Analog/RF applications. And these optimizations yields CLDMOS power amplifier with 36 dB gain, 800 MHz bandwidth and 46.4% efficiency. Comparing with existing structure a good improvement of gain and bandwidth has been observed.
- 出版日期2014-8
