Digital LDO with 1-bit ΔΣ modulation for low-voltage clock generation systems

作者：Song, Haixin; Rhee, Woogeun^*; Shim, Inbo; Wang, Zhihua

来源：Electronics Letters, 2016, 52(25): 2034-2035.

DOI：10.1049/el.2016.2982

• Clock generation system
• Hardware complexity
• Load currents
• Low dropout regulator
• Low voltages
• Output voltages
• Proposed architectures
• Transistor arrays

A coarse-fine dual-loop digital low dropout regulator (DLDO) having a binary weighed transistor array in the coarse loop and a 1-bit Delta Sigma modulator in the fine loop is proposed. Compared with the conventional DLDO, the proposed architecture significantly reduces hardware complexity and alleviates matching requirement, enabling a robust DLDO design for low-voltage phase-locked loops. The proposed DLDO designed in 65 nm CMOS generates a noise-shaped output voltage whose peak value is <1 mV with the load current ranging from 100 mu A to 6 mA.

• 出版日期2016-12-8
• 单位清华大学