Accurate and Affordable Packet-Train Testing Systems for Multi-Gigabit-per-Second Networks

作者：Ruiz Mario^*; Ramos Javier^*; Sutter Gustavo^*; Lopez de Vergara Jorge E; Lopez Buedo Sergio^*; Aracil Javier^*

来源：IEEE Communications Magazine, 2016, 54(3): 80-87.

DOI：10.1109/mcom.2016.7432152

Communication networks these days face a relentless increase in traffic load. Multi-gigabit-per-second links are becoming widespread, and network devices are under continuous stress, so testing whether they guarantee the specified throughput or delay is a must. Software-based solutions, such as packet-train traffic injection, were adequate for lower speeds, but they have become inaccurate in the current scenario. Hardware-based solutions have proved to be very accurate, but usually at the expense of much higher development and acquisition costs. Fortunately, new affordable FPGA SoC devices, as well as high-level synthesis tools, can very efficiently reduce these costs. In this article we show the advantages of hardware-based solutions in terms of accuracy, comparing the results obtained in an FPGA SoC development platform and in NetFPGA-10G to those of software. Results show that a hardware-based solution is significantly better, especially at 10 Gb/s. By leveraging high-level synthesis and open source platforms, prototypes were quickly developed. Noticeable advantages of our proposal are high accuracy, competitive cost with respect to the software counterpart, which runs in high-end off-the-shelf workstations, and the capability to easily evolve to upcoming 40 Gb/s and 100 Gb/s networks.

• 出版日期2016-3