A Small Size 100 MHz to 13.4 GHz Fractional-N RF Synthesizer for RF ATE Based on 13-band VCOs and 48-bit Delta Sigma Modulator

作者：Kimishima Masayuki^*; Sakai Hidenori; Nagami Haruki; Utamaru Goh; Shirasu Hideki; Kogami Yoshinori

来源：IEICE TRANSACTIONS ON ELECTRONICS, 2013, E96C(10): 1227-1235.

DOI：10.1587/transele.E96.C.1227

• RF test
• ATE
• VCO
• SIP
• Delta Sigma modulator
• IIR filter

This paper describes a small size broadband fractional-N RF synthesizer for an RF test module with a high throughput and multiple resources installed in RIP Automated Test Equipment (ATE) systems. The core device is the PLL-LSI composed of the 13-band asymmetrical tournament form voltage-controlled oscillators (VCOs) and the proposed 48-bit Delta Sigma modulator with the infinite impulse response (IIR) filter. The single-loop PLL RF synthesizer is constructed in the form of systems in package (SiP) including the PLL-LSI and the active loop filter. The RIP synthesizer SiP features a small size of 20 mm x 20 mm x 3 mm, a high frequency resolution of smaller than 50 mu Hz, and a phase noise of better than -110 dBc/Hz at offset frequency of 1 MHz across a frequency range of 100 MHz to 13.4 GHz. In addition, a frequency settling time of 150 mu s that is faster than our conventional dual-loop PLL synthesizers using the discrete VCOs or the YIG-tuned oscillators (YTOs) is achieved. The synthesizer SiP significantly contributes to the realization of small size, high throughput RF test modules for RIP ATEs.

• 出版日期2013-10