A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique

作者：Zhang, Zhao; Yang, Jincheng; Liu, Liyuan; Feng, Peng; Liu, Jian; Wu, Nanjian^*

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018, 26(5): 933-944.

DOI：10.1109/TVLSI.2018.2797280

• Hybrid digital
• loop bandwidth tracking
• low-power
• low-voltage
• phase-locked loop (PLL)
• power efficiency

This paper proposes a low-voltage low-power hybrid digital phase-locked loop (LVHDPLL). It adopts a loop bandwidth-tracking technique to keep the loop bandwidth almost constant in order to make the LVHDPLL operate robustly over process, voltage, and temperature variation. We also propose the technique of dynamical control of clock frequency for digital loop filter, and the gated source-switched charge pump to save the power consumption. The LVHDPLL is implemented in a 65-nm CMOS process. It can generate frequency from 0.9 to 2.25 GHz (1.35 GHz) at 0.75-V (0.6 V) supply voltage. The maximum power consumption is 0.43mW at 0.75 V and 0.21 mW at 0.6 V. The power efficiency is 0.191 and 0.156 mW/GHz at 0.75- and 0.6-V supply, respectively. The figure of merit is -228 and -227.4 dB at 0.75- and 0.6-V supply, respectively. The loop bandwidth variation over all covered frequency range is +/- 7.5%. From 0 degrees C to 70 degrees C, the loop bandwidth variation and rms jitter variation are less than 6.1% and 8.8%, respectively. The loop bandwidth variation and rms jitter variation over supply variation (-0.03 to 0.05 V) is less than 7.1% and 9.5%, respectively. This LVHDPLL shows robustness over temperature and supply voltage variation.

• 出版日期2018-5
• 单位中国科学院; 中国科学院大学