A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits

作者：Iwata Kenichi^*; Irita Takahiro; Mochizuki Seiji; Ueda Hiroshi; Ehama Masakazu; Kimura Motoki; Takemura Jun; Matsumoto Keiji; Yamamoto Eiji; Teranuma Tadashi; Takakubo Katsuji; Watanabe Hiromi; Yoshioka Shinichi; Hattori Toshihiro

来源：IEEE Journal of Solid-State Circuits, 2010, 45(1): 59-68.

DOI：10.1109/JSSC.2009.2031797

• Address translation
• application processor
• dynamic clock control
• full HD video
• memory bandwidth
• mobile phone
• video codec

A full-HD (1080p30) 500 MHz mobile application processor with an H.264 HP/MPEG-2/MPEG-4 video codec is integrated on a 6.4 x 6.5 mm(2) die in 65 nm low-power CMOS. With two parallel pipelines for macroblock processing and tile-based address translation circuits, the processor consumes 342 mW in real-time playback of a full-HD H.264 stream from a 64 b width low-power DDR-SDRAM at an operating frequency of 166 MHz at 1.2 V.

• 出版日期2010-1